A development cost of a semiconductor device is increasing, and instead of developing a die with a large area, a method of reducing the development cost by functional decomposition has come to be required. In view of lowering a cost of an entire system, a semiconductor device of three-dimensional structure in which dies are stacked attracts attention. As illustrated in FIG. 5 as an example, it is possible to curtail a system area by mounting a top die 51 of dies and the like of a memory circuit above a bottom die 52 of dies and the like of a processor core circuit, for example.
In the semiconductor device of three-dimensional structure, data transmission between dies is carried out by using a through silicon via (TSV) 53 penetrating a semiconductor substrate 52S, and a micro-bump 54. By connecting a plurality of dies by using the through silicon via to shorten a transmission distance of a data signal, data transmission at a high speed and at a low power can be realized, so that it becomes possible to carry out information processing efficiently. In FIG. 5, a reference numeral 55 indicates a solder bump for package connection. In a case where a die is mounted further above the top die 51, a through silicon via penetrating a semiconductor substrate 51S is provided, and data transmission is carried out by using that through silicon via and a micro-bump.
Not only a shape parameter value in manufacturing a through silicon via penetrating a semiconductor substrate but also electric characteristic values of the through silicon via such as a resistance characteristic (R), an inductor characteristic (L), and a capacity characteristic (C) are different depending on a semiconductor foundry. Also the through silicon via has a problem that the characteristic value of the through silicon via fluctuates dynamically during an operation of a semiconductor device due to its structure. For example, a barrier layer is provided between the semiconductor substrate and the through silicon via penetrating the semiconductor substrate, and a structure equivalent to a transistor is formed by the semiconductor substrate, the barrier layer, and the through silicon via. Therefore, when a signal is transmitted via the through silicon via, there is a possibility that capacity fluctuation in a through silicon via occurs in correspondence with a frequency of the transmitted signal (MIS (Metal-Insulator-Semiconductor) effect), whereby delay of a transmission path which includes the through silicon via sometimes fluctuates dynamically.
In general, in designing a semiconductor device, when extraction of parameters such as a resistance and a capacity of a MOS transistor, a metal wiring or the like is carried out, the extraction is simply based on a shape of a device only. For example, in an electronic design automation (EDA) tool as of now, a through silicon via being not regarded as a column-shaped transistor, a characteristic is extracted based on a three-dimensional shape, and thus it is not possible to carry out automatic placement and routing, calculation of a delay value or the like in which fluctuation of a characteristic due to various actions occurring by the MIS effect or the like is taken into consideration. Consequently, a user of the semiconductor device conceives various calculation formulas and calculates characteristic values based on semiconductor parameters in order to investigate characteristics of the through silicon via, then creates test chips numerous times, and compares and evaluates calculation values and actual characteristic values of the through silicon via having been measured, thereby to figure out an RLC characteristic of the through silicon via of an actual chip. However, this method leads to an increase in development cost.
It is general that a foundry does not disclose a characteristic value of a semiconductor which relates to a performance of a semiconductor device, and it is quite difficult for a user designing the semiconductor device to obtain such characteristic parameter values. In a case where a through silicon via is manufactured by OSAT (outsource assembly and test) or the like, the characteristic depends also on a manufacturing method thereof. Consequently, there occurs a state where the user designing the semiconductor device cannot confirm or control characteristic fluctuation of the through silicon via. Under certain circumstances, respin (redesign) of the semiconductor device is also required due to characteristic fluctuation of the through silicon via, which leads to increases in entire design cost and design time.
In order to suppress fluctuation of a capacity value of a through silicon via, there is suggested a method in which the through silicon vias are created in correspondence with kinds of signals transmitted by the through silicon vias, and a method in which the through silicon via has a special structure to suppress capacity fluctuation (for example, see Patent Documents 1, 2). However, creating the through silicon vias individually or making the through silicon via having the special structure leads to an increase in area or an increase in cost.
[Patent Document 1] U.S. Patent Application Publication No. 2014/0008800
[Patent Document 2] U.S. Patent Application Publication No. 2014/0054742
When a capacity value of a through silicon via fluctuates dependently on a frequency of a signal passing through the through silicon via, an RC characteristic of a transmission path which includes the through silicon via changes and a delay value fluctuates, so that a propagation velocity of the signal changes. Consequently, there is an apprehension that signal transmission between dies fails. One of causes for the above problem is that continuation of the same data in the signals transmitted by the through silicon via makes the frequencies of the signals low. When the same data continues, the frequencies of the signals flowing on a signal line of that one bit become low apparently, so that a capacity of the through silicon via becomes large by an MIS effect. For example, a capacity value at a time of low frequency signal becomes three to five times as large as a capacity value at a time of high frequency signal. Consequently, a differential delay corresponding to a repetition rate of change of data occurs dependently on a pattern of data to be transmitted, and there is a possibility that signal transmission between dies fails.
If characteristic fluctuation due to the MIS effect can be estimated, it is possible to cope with the above by executing a simulation or the like at a time of designing. However, as described above, it is often the case that a characteristic value (parameter value) of a semiconductor which is necessary for verifying the MIS effect is not disclosed, and a user designing a semiconductor device is often unable to obtain those characteristic values. Though there is a method of suppressing characteristic fluctuation by the structure of the through silicon via as described above, that method leads to an increase in area or an increase in cost.